FPGA Implementation of IP-core of FFT Block for DSP Applications
نویسندگان
چکیده
This paper discuss about FPGA implementation of radix-4 FFT algorithm, which is simulated ,synthesized, and downloaded on xcv1000 FPGA, which gives the operating speed of 52.3 MHz. Fourier transform play an important role in many digital signal processing applications including acoustics, optics, telecommunications, speech, signal and image processing. However, their wide use makes their computational requirements a heavy burden in much real world application. Direct computation on discrete Fourier transform requires on the order of N2 operations, where N is the transform size. Most of the research to date for the implementation and bench -marking of FFT algorithm has been performed using general purpose processors. Reconfigurable hardware, usually in the form of FPGA has been used as a new and better means of performing high performance computing. Reconfigurable computing systems are those computing platforms whose architecture can be modified to suit the application at the hand.
منابع مشابه
The Design and Implementation of FFT Algorithm Based on The Xilinx FPGA IP Core
This paper introduces a kind of FFT algorithm design and realization based on the Xilinx IP core . On the analysis of FFT algorithm, Rely on Xilinx Spartan -3A DSP FPGA series as platform, by calling FFT IP core, validating the feasibility and reliability in FFT algorithm medium or lower end FPGA. Keywords-FFT algorithm module, Xilinx IP core, Spartan 3A DSP, Fixed-point compression
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